This invention relates to semiconductor processing methods of forming contact openings, methods of forming memory circuitry, methods of forming electrical connections, and methods of forming dynamic random access memory (DRAM) circuitry.
Semiconductor processing typically involves a number of processing steps including material deposition, masking with masking layers, and etching to define integrated circuitry structures. At each processing step there are risks that the integrated circuitry being formed can be compromised. As the complexity of integrated circuitry increases, so too can the processing complexities and the risk that the formed circuitry will be compromised. One of the factors that contributes to the risk of compromised integrated circuitry is the number of masking steps that are used in a particular processing flow. The more masking steps, the more the likelihood is that a misalignment can occur. Another problem which has implications insofar as device integrity is concerned relates to conductive material undesirably remaining behind over wafer areas. Such remnant material is sometimes referred to as xe2x80x9cstringersxe2x80x9d and can cause device components to short to one another. Accordingly, there is a need within the industry to reduce the likelihood that these and other problems will affect the integrated circuitry being formed.
This invention arose out of concerns associated with improving the methods by which integrated circuitry is formed and reducing the risks that the formed circuitry will be compromised.
Methods of forming contact openings, memory circuitry, and dynamic random access memory (DRAM) circuitry are described. In one implementation, an array of word lines and bit lines are formed over a substrate surface and separated by an intervening insulative layer. Conductive portions of the bit lines are outwardly exposed and a layer of material is formed over the substrate and the exposed conductive portions of the bit lines. Selected portions of the layer of material are removed along with portions of the intervening layer sufficient to (a) expose selected areas of the substrate surface and to (b) re-expose conductive portions of the bit lines. Conductive material is subsequently formed to electrically connect exposed substrate areas with associated conductive portions of individual bit lines.